Xilinx rtl schematic not updating

I'm working on a project using Xilinx ISE on my PC and it's version 14.x When I try to open the project at the university computers which have Xilinx 12.x installed, I get an error that I can't open projects created using later versions of Xilinx.

Is there any way to do something like Save As older Xilinx project or maybe a way to convert new Xilinx project to older one?

Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx.

Xilinx assumes noobligation to correct any errors contained herein or to advise you of any correction if such be made.

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THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU.Xilinx recommends Vivado® Design Suite for new design starts with Virtex®-7, Kintex®-7, Artix®-7, and Zynq®-7000.



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